The present invention generally relates to semiconductor manufacturing and more particularly to fabricating reworkable interconnect structures having integrated testing capabilities.
Typical semiconductor integrated circuit (IC) chips may have layers stacked such that layer features overlay one another to form individual devices and connect devices together. ICs are mass produced by forming an array of chips on a thin semiconductor wafer. Each array location is known as a die and each die may harbor a multilayered structure, such as an IC chip or a structure for test or alignment.
As transistor technologies advance, chip features and devices are increasingly smaller having minimum dimensions that may be well below one micrometer (1 μm) or 1 micron. Smaller chip features and devices allow IC manufacturers to integrate more function in the same chip real estate. However, scaling of wafer test probes to finer pitch may pose numerous challenges, as the cost and complexity of wafer probe technology increases. By way of example, in existing approaches, challenges in test probe manufacturing may include scalability, material selection flexibility, and cost of fabrication. Probe card and test probe technologies have been adapted to cover area array interconnection pitches down to the range of 150-200 microns. These technologies may not offer a workable solution for fine-pitch probing in three-dimensional (3D) silicon devices with area array pitches 50 microns and smaller.